Index of /archive1/MESSEPPSDATA_3001/DATA/EPS_PITCH_ANGLES/2014/JAN

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[PARENTDIR] Parent Directory                                                             -   
[   ] EPSP_A2014001DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014001DDR_V4.TAB                                 2016-03-22 22:45  6.9M  
[   ] EPSP_A2014002DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014002DDR_V4.TAB                                 2016-03-22 22:45  6.9M  
[   ] EPSP_A2014003DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014003DDR_V4.TAB                                 2016-03-22 22:45  4.4M  
[   ] EPSP_A2014004DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014004DDR_V4.TAB                                 2016-03-22 22:45  470K  
[   ] EPSP_A2014005DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014005DDR_V4.TAB                                 2016-03-22 22:45  470K  
[   ] EPSP_A2014006DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014006DDR_V4.TAB                                 2016-03-22 22:45  470K  
[   ] EPSP_A2014007DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014007DDR_V4.TAB                                 2016-03-22 22:45  4.0M  
[   ] EPSP_A2014008DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014008DDR_V4.TAB                                 2016-03-22 22:45  4.7M  
[   ] EPSP_A2014009DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014009DDR_V4.TAB                                 2016-03-22 22:45  4.7M  
[   ] EPSP_A2014010DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014010DDR_V4.TAB                                 2016-03-22 22:45  4.7M  
[   ] EPSP_A2014011DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014011DDR_V4.TAB                                 2016-03-22 22:45  4.7M  
[   ] EPSP_A2014012DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014012DDR_V4.TAB                                 2016-03-22 22:45  4.7M  
[   ] EPSP_A2014013DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014013DDR_V4.TAB                                 2016-03-22 22:45  4.7M  
[   ] EPSP_A2014014DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014014DDR_V4.TAB                                 2016-03-22 22:45  5.7M  
[   ] EPSP_A2014015DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014015DDR_V4.TAB                                 2016-03-22 22:45  6.9M  
[   ] EPSP_A2014016DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014016DDR_V4.TAB                                 2016-03-22 22:45  6.9M  
[   ] EPSP_A2014017DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014017DDR_V4.TAB                                 2016-03-22 22:45  6.9M  
[   ] EPSP_A2014018DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014018DDR_V4.TAB                                 2016-03-22 22:45  6.9M  
[   ] EPSP_A2014019DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014019DDR_V4.TAB                                 2016-03-22 22:45  6.9M  
[   ] EPSP_A2014020DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014020DDR_V4.TAB                                 2016-03-22 22:45  6.9M  
[   ] EPSP_A2014021DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014021DDR_V4.TAB                                 2016-03-22 22:45  5.7M  
[   ] EPSP_A2014022DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014022DDR_V4.TAB                                 2016-03-22 22:45  4.5M  
[   ] EPSP_A2014023DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014023DDR_V4.TAB                                 2016-03-22 22:45  4.5M  
[   ] EPSP_A2014024DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014024DDR_V4.TAB                                 2016-03-22 22:45  4.2M  
[   ] EPSP_A2014025DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014025DDR_V4.TAB                                 2016-03-22 22:45  4.5M  
[   ] EPSP_A2014026DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014026DDR_V4.TAB                                 2016-03-22 22:45  4.5M  
[   ] EPSP_A2014027DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014027DDR_V4.TAB                                 2016-03-22 22:45  4.5M  
[   ] EPSP_A2014028DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014028DDR_V4.TAB                                 2016-03-22 22:45  5.7M  
[   ] EPSP_A2014029DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014029DDR_V4.TAB                                 2016-03-22 22:45  4.5M  
[   ] EPSP_A2014030DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014030DDR_V4.TAB                                 2016-03-22 22:45  4.5M  
[   ] EPSP_A2014031DDR_V4.LBL                                 2016-03-22 21:59  2.4K  
[   ] EPSP_A2014031DDR_V4.TAB                                 2016-03-22 22:45  4.3M